4. Testcase Generation, Simulation and RCA Debugging Workflow

This workflow covers automatic generation of sequences and testcase code, VCS simulation runs, blocking-level lint fixes, root cause analysis of simulation failures, and extraction of FSDB binary waveform data for waveform-based root cause location.

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Orchestration Skill: uvm-testcase-auto

uvm-testcase-auto orchestrates the complete testcase and simulation stage. It never generates multiple testcases at once: each TC goes through generate ➔ compile and simulate ➔ auto-fix in turn, with the status of every TC reported as it runs, and a full test report produced at the end.

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Skills in Detail

1. uvm-env-base-seq-gen — Base and Smoke Sequence Generation

• What it does: generates the UVM UVC base sequence ({ip_name}_base_sequence) and smoke sequence ({ip_name}_smoke_sequence) files for a given IP.

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2. uvm-testcase-gen-testcase — Testcase Generation and SVA Suppression

• What it does: generates the TC class and virtual sequence for a single UVM testcase from the test plan, registers the header into the `include list in tbench.v, incrementally updates the scoreboard per the checkpoint requirements, and consults sva_index.md for the [SVA-cover] / [SVA-off] tags on each test point to decide whether $assertoff / $asserton control is written into the virtual sequence.
• Usage: /uvm-testcase-gen-testcase <WORK_DIR> <TESTPLAN_MD> [TC_NAME]

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3. uvm-testcase-compile-sim — VCS Compilation and Simulation

• What it does: fixes blocking-level lint errors in the testcase's own files before the run, then invokes VCS for compilation and headless simulation, parses the logs and emits a structured PASS or FAIL result.
• Usage: /uvm-testcase-compile-sim <WORK_DIR> <TC>

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4. uvm-testcase-debug-failure — Simulation Failure Log RCA

• What it does: diagnoses UVM compilation and simulation failures. Compilation errors are fixed automatically by the AI, limited to TC/env files and at most three rounds. Simulation errors produce a structured root cause analysis report; source files and RTL are never modified.
• Usage: /uvm-testcase-debug-failure <WORK_DIR> <TC>

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5. uvm-testcase-wave-rca — Iterative FSDB Waveform Root Cause Analysis

• What it does: when a testcase fails — a hang, a scoreboard mismatch, a triggered assertion — it runs a chained analysis of log first, then waveform evidence, then RTL drill-down, and emits a structured root cause report. It does not modify RTL, testbench or VIP.
• Usage: /uvm-testcase-wave-rca <WORK_DIR> <TC> <RTL>

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6. uvm-fsdb-wave-extract — FSDB Transition History Extraction

• What it does: calls the Verdi Python NPI interface to extract the transition history of specified signals within a given time window from the FSDB binary waveform, emitting a compact JSON structure for use as waveform evidence during diagnosis.
• Usage: /uvm-fsdb-wave-extract <FSDB> <TOP> <START> <END> <SIGNALS> <MAX_CHANGES> <OUTPUT>