Skill Dependencies and Data Flow

Every skill on the Forenyx platform follows an explicit input/output contract. Configuration files and code artifacts produced upstream become the input for downstream skills.

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1. Global Dependency Topology

The diagram below shows how data flows between skills across the verification process:

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2. Skill Input/Output Contracts

Skill	Prerequisite skill	Input files / data	Output artifacts
ic-docx2md	None	$0 input .docx $1 output .md	.md document + extracted image directory
ic-audit-spec	ic-docx2md	$0 design spec .md $1 register .xml (IP-XACT)	FSM logic review report .md Spec quality review report .md
ic-audit-prd-spec	ic-docx2md	$0 register .xml $1 design spec .md $2 PRD .yaml $3 output path (optional)	spec_review_result.md
ic-audit-soc-spec	ic-docx2md	$0 SoC spec .md $1 chip register description .svd/.xml (optional) $2 report output directory (optional)	Three SoC spec quality review reports .md — IP level, connection level, system level
ic-audit-soc-prd-spec	ic-docx2md	$0 SoC integration spec .md $1 SoC PRD .yaml $2 chip register description (optional) $3 output path (optional)	soc_review_result.md
ic-audit-design-auto	ic-docx2md	$0 design spec .md $1 register .xml $2 PRD .yaml $3 report output path (optional)	Orchestrates ic-audit-prd-spec + ic-audit-spec Staged review reports (pauses after each stage)
ic-gen-hal	ic-docx2md	$0 design spec .md $1 register .xml (optional) $2 IP module name $3 output path (optional)	{IP}_hal.md
uvm-testplan-gen-feature	ic-docx2md	$0 register .xml $1 IP design document .md $2 output path (optional)	uvm_feature_report.md
uvm-testplan-gen-testplan	uvm-testplan-gen-feature	$0 feature report .md $1 design spec .md $2 design source RTL/Chisel (optional) $3 output path (optional)	uvm_testplan.md
uvm-testplan-auto	ic-docx2md	$0 register .xml $1 IP design document .md $2 design source RTL/Chisel (optional) $3/$4 feature / test plan output paths (optional)	Orchestrates gen-feature + gen-testplan uvm_feature_report.md + uvm_testplan.md
uvm-env-create	None	$0 IP_NAME $1 TC_NAME $2 WORK_DIR $3 register .xml	UVM skeleton directory + smoke test
uvm-env-cfg	uvm-env-create	No positional arguments (triggered while editing *_env.sv / *_env_cfg.sv)	{ip}_env.sv, {ip}_env_cfg.sv
uvm-env-config-db	uvm-env-create	No positional arguments (triggered while editing *_config_db.sv)	{ip}_config_db.sv (virtual interface and config object injection via uvm_config_db::set)
uvm-env-inf-connect	uvm-env-create	$0 IP_NAME $1 WORK_DIR $2 top-level RTL .v/.sv $3 VIP_DIR (optional)	{ip}_inf_connect.sv
uvm-env-impl	uvm-env-create	$0 IP_NAME $1 WORK_DIR $2 top-level RTL .v/.sv $3 spec .md $4 testplan .md $5 VIP_DIR (optional)	Driver / Monitor / Scoreboard / coverage implementation
uvm-env-sva	uvm-testplan-gen-testplan	$0 IP_NAME $1 WORK_DIR $2 top-level RTL .v/.sv $3 testplan .md $4 spec .md (optional) $5 FSM coverage directory (optional)	sim/sva/*.sv, sva_bind.sv sva_index.md, signal_manifest.json
uvm-env-base-seq-gen	uvm-env-create	No positional arguments (triggered by IP name and protocol)	{ip}_base_sequence.sv {ip}_smoke_sequence.sv
uvm-testcase-gen-testcase	uvm-testplan-gen-testplan	$0 WORK_DIR $1 testplan .md $2 TC_NAME (optional, prompts if omitted)	TC class, virtual sequence tbench.v include registration
uvm-testcase-auto	uvm-testplan-gen-testplan	$0 WORK_DIR $1 testplan .md	Orchestrates gen-testcase + compile-sim + debug-failure Per-TC closed loop + summary report Writes generation status back to the testplan
uvm-testcase-compile-sim	uvm-testcase-gen-testcase	$0 WORK_DIR $1 TC name	com.log / run.log PASS / FAIL verdict
uvm-testcase-debug-failure	uvm-testcase-compile-sim	$0 WORK_DIR $1 TC name	Auto-fix for compile errors (TC/env, max 3 rounds) RCA report for simulation errors
uvm-testcase-wave-rca	uvm-testcase-compile-sim	$0 WORK_DIR $1 TC name $2 RTL file or directory	Waveform RCA report
uvm-fsdb-wave-extract	uvm-testcase-compile-sim	$0 FSDB path $1 top scope (optional) $2/$3 start/end time (optional) $4 signal names $5 max transitions (optional) $6 output path (optional)	Signal transition history JSON
uvm-coverage-closure	uvm-testcase-compile-sim	$0 WORK_DIR $1 testplan .md $2 RTL directory --spec / --extra-points / --target-func / --target-code / --exclude-modules (all optional)	Coverage gap report with two human-decision tables (suspected dead code; coverage-model build) [coverage-driven] entries appended to testplan Coverage-model build list
uvm-env-coverage-add	uvm-coverage-closure uvm-env-impl	$0 WORK_DIR $1 testplan .md $2 RTL directory --from-report / --categories / --spec / --max-groups (all optional)	Incrementally added covergroups (edits {IP}_coverage.sv only) Verified by a COV=1 compile
uvm-progress-tracker	uvm-testplan-gen-testplan	$0 stage name (optional; append mode when given) $1 coverage 0-100 (optional) --file / --start-time / --rpt-dir (optional)	uvm_progress.json (each stage carries start_time / finish_time / duration)
uvm-progress-chart	uvm-progress-tracker	$0 stage data JSON $1 output directory $2 filename prefix (optional)	Trend line chart .drawio + .png
uvm-report-gen	uvm-coverage-closure uvm-testcase-auto	$0 WORK_DIR $1 output .docx --ledger DUT defect ledger (strongly recommended) --rpt-dir / --testplan / --spec / --rtl-dir / --kb / --progress / --outline (optional)	Formal verification report .docx (screenshots left as placeholder boxes) Data-reconciliation notes + open-item list
uvm-report-gen-qmd	same as uvm-report-gen	$0 WORK_DIR $1 output directory --formats / --assets-dir / --reference-docx remaining arguments as for uvm-report-gen	.qmd source + .docx + .html (+ .pdf) Missing-figure list + data-reconciliation notes + open items

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3. Core Data Handoffs

3.1 Test Plan Attribute Tags

uvm_testplan.md records each feature together with the mechanism that checks it:

• [CSR] — covered by UVM RAL read/write tests.
• [Scoreboard] — the scoreboard compares expected against actual values.
• [SVA-cover] — coverage is collected by an SVA cover module.
• [SVA-off] — instructs uvm-testcase-gen-testcase to emit $assertoff() suppression.

3.2 Interface and Data Flow Contracts

• Monitor ➔ Scoreboard — the monitor samples bus transactions and broadcasts them through an analysis port into the scoreboard comparison FIFO.
• Sequence ➔ Driver — sequence items travel through the sequencer to the driver, which drives the interface.
• SVA ➔ DUT — SVA checker modules attach to internal DUT signals through the SystemVerilog bind construct.

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4. Troubleshooting

4.1 Missing uvm_testplan.md

If testcase generation is invoked without a test plan, the system falls back to generic baseline testcases derived from the interface definition. Feature-specific configuration is not possible in this mode.

4.2 SVA Binding and Hierarchy Errors

If compilation reports that the assertion hierarchy is unavailable, confirm that:

• uvm-env-sva has been run and produced sva_bind.sv;
• sva_bind.sv has been added to the compilation filelist.f.