3. UVM Environment and Assertion Build-Out Workflow

This workflow covers UVM environment scaffolding, signal interface connection, configuration database injection, implementation of the functional components, and non-intrusive generation and binding of the always-on SVA checker layer.

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Architecture and Component Model

Within a UVM verification environment, the base framework and the assertion checker layer are built as follows:

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Skills in Detail

1. uvm-env-create — Framework Creation and Smoke Test

• What it does: generates the UVM environment skeleton for a given IP (tb/, env/, agents/) and runs a smoke test to confirm the framework compiles and starts. It does not verify DUT functionality.
• Input: the IP name and interface description.

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2. uvm-env-config-db — Configuration Objects and Virtual Interface Injection

• What it does: writes or modifies *_config_db.sv, injecting the virtual interfaces and configuration objects instantiated in the simulation top tb_top into the corresponding UVM components through uvm_config_db::set. Supports AXI/AHB/APB/TileLink/SPI, in both IP-level and chip-level configuration modes.

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3. uvm-env-inf-connect — Interface Connection File Generation

• What it does: generates {ip}_inf_connect.sv from the DUT RTL port list and the bus protocol type, wiring the VIP/UVC to the DUT physical signals.
• Modes and protocols: IP level (active stimulus) and chip level (passive monitoring), covering AXI/AHB/APB/TileLink/SPI/I2C/UART and local interfaces.

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4. uvm-env-impl — Environment Implementation

• What it does: builds on the skeleton produced by uvm-env-create. Using the DUT RTL, the design spec and any existing VIP/UVC, it fills in interface signals, transaction fields, driver logic, monitor sampling, the scoreboard comparison model and coverage; it then patches the env/tbench/top_env connection layer so the environment compiles and runs, and finally invokes uvm-env-sva to generate the SVA layer.

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5. uvm-env-sva — SVA Checker Generation and Bind Attachment

• What it does: analyzes the SVA checking intent declared in testplan.md, discovers the real signals from the RTL sources (emitting signal_manifest.json), generates always-on SVA checker modules under sim/sva/*.sv plus a non-intrusive sva_bind.sv, and appends the include to tbench.v.
• Boundaries: creates SVA only under sim/sva/ and attaches it through the SystemVerilog bind construct. It never modifies RTL sources or VIP. Real signal paths are resolved by parsing the RTL with discover_signals.py.