Skill Matrix

The Forenyx platform includes 29 skills, each focused on a specific verification task. This page indexes every skill together with its data contract and the workflow it belongs to.

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Contract Reference for All 28 Skills

Skill	Category	Input ➔ output contract	Workflow
ic-docx2md	Spec extraction	.docx / .pdf document ➔ Markdown spec and image directory	1. Spec audit
ic-audit-spec	Architecture audit	Spec.md ➔ FSM logic and spec quality report	1. Spec audit
ic-audit-prd-spec	Requirement diff	PRD.md + Spec.md ➔ structured requirement report	1. Spec audit
ic-audit-soc-prd-spec	Requirement diff	SoC PRD.yaml + SoC integration Spec.md + chip register description (optional) ➔ SoC-level requirement report	1. Spec audit
ic-audit-soc-spec	Architecture audit	SoC integration Spec.md + chip register description (optional) ➔ three SoC spec quality reports: IP, connectivity, system	1. Spec audit
ic-audit-design-auto	Orchestration	PRD.md + Spec.md ➔ staged audit reports	1. Spec audit
ic-gen-hal	Code generation	Spec.md + register .xml ➔ HAL documentation	1. Spec audit
uvm-testplan-gen-feature	Test planning	Spec.md + register .xml ➔ feature report .md	2. Test planning
uvm-testplan-gen-testplan	Test planning	Reviewed feature report .md ➔ uvm_testplan.md	2. Test planning
uvm-testplan-auto	Orchestration	Spec.md ➔ feature report and uvm_testplan.md	2. Test planning
uvm-env-create	Environment	IP name + interface spec ➔ UVM skeleton and smoke test	3. Environment
uvm-env-cfg	Environment	Config parameter declaration ➔ *_config_db.sv object	3. Environment
uvm-env-config-db	Environment	tb_top virtual interface ➔ uvm_config_db::set injection	3. Environment
uvm-env-inf-connect	Environment	RTL port list ➔ {ip}_inf_connect.sv interface file	3. Environment
uvm-env-impl	Environment	RTL + Spec + VIP ➔ complete Driver/Monitor/Scoreboard	3. Environment
uvm-env-sva	Assertions	testplan.md + RTL ➔ sim/sva/*.sv & bind	3. Environment
uvm-env-coverage-add	Environment	Coverage-model build list + testplan.md ➔ incremental covergroups in {ip}_coverage.sv (compiled with COV=1; no simulation)	5. Coverage closure
uvm-env-base-seq-gen	Sequences	IP name + protocol ➔ {ip}_base/smoke_sequence.sv	4. Testcase and simulation
uvm-testcase-gen-testcase	Testcases	testplan.md + [TC_NAME] ➔ TC class & virtual seq	4. Testcase and simulation
uvm-testcase-compile-sim	VCS simulation	WORK_DIR + [TC_NAME] ➔ lint fix, VCS run, logs	4. Testcase and simulation
uvm-testcase-debug-failure	Log RCA	com.log / run.log ➔ auto compile fix or RCA report	4. Testcase and simulation
uvm-testcase-wave-rca	Waveform RCA	FSDB waveform + run.log ➔ iterative root cause report	4. Testcase and simulation
uvm-fsdb-wave-extract	Waveform extract	FSDB waveform + signal name ➔ transition history JSON	4. Testcase and simulation
uvm-testcase-auto	Orchestration	WORK_DIR + testplan.md ➔ per-TC generate, compile, report	4. Testcase and simulation
uvm-coverage-closure	Coverage	VCS coverage report ➔ gap analysis report (two human-decision tables) + testplan additions	5. Coverage closure
uvm-progress-tracker	Verification mgmt	Regression / coverage data ➔ maintains uvm_progress.json (per-stage start_time / duration)	5. Coverage closure
uvm-progress-chart	Visualization	Progress JSON ➔ trend line chart (.drawio + .png)	5. Coverage closure
uvm-report-gen	Verification report	Coverage report + defect ledger + testplan.md + RTL ➔ formal verification report .docx (with cross-checked figures and open items)	5. Coverage closure
uvm-report-gen-qmd	Verification report	The same, rendered through Quarto ➔ one source producing .docx + .html (+ .pdf), with a TOC, numbered tables/figures and cross-references	5. Coverage closure

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Workflows at a Glance

1. Architecture Design and Requirement Audit

Includes ic-docx2md, ic-audit-spec, ic-audit-prd-spec, ic-audit-soc-prd-spec, ic-audit-soc-spec, ic-gen-hal, ic-audit-design-auto.

2. Test Plan Automation

Includes uvm-testplan-gen-feature, uvm-testplan-gen-testplan, uvm-testplan-auto.

3. UVM Environment and Assertions

Includes uvm-env-create, uvm-env-cfg, uvm-env-config-db, uvm-env-inf-connect, uvm-env-impl, uvm-env-sva.

4. Testcases, Simulation and RCA Debugging

Includes uvm-env-base-seq-gen, uvm-testcase-gen-testcase, uvm-testcase-compile-sim, uvm-testcase-debug-failure, uvm-testcase-wave-rca, uvm-fsdb-wave-extract, uvm-testcase-auto.

5. Coverage Closure and Progress Tracking

Includes uvm-coverage-closure, uvm-env-coverage-add, uvm-progress-tracker, uvm-progress-chart, uvm-report-gen, uvm-report-gen-qmd.